Senior DFT Engineer

A Semiconductor industry Design for Test (DFT) Engineer will take responsibility for driving the design implementation and simulations through to successful tape-out for an innovative market leader revolutionizing the electronics industry.
Technical Competencies for the Semiconductor DFT Engineer:
* Minimum of a good Bachelors degree in Electronics or similar discipline.
* 5+ years Design For Test (DFT) experience.
* Experience with MBIST insertion, simulation and verification on RTL and Gate level Netlist.
* Experience with Scan insertion.
* Good knowledge of Verilog HDL.
* Hands-on experience using EDA tools for DFT such as Cadence, Mentor or Synopsys.
* STA DFT test mode timing constraint development and analysis.
* TCL Scripting.
The Design for Test (DFT) Engineer role: The successful DFT Engineer will drive architectures, methodologies and tool flows for complex multi-million gate designs. With a good understanding of ATE, you’ll drive the test engineering team for successful Silicon bring up and test program development; will define the test plans and develop functional tests for final/wafer test program development.
A generous salary will be offered depending on your level of experience with Shares on offer, Hybrid working and flexible working.
This company ensures diversity and inclusion for all, as well prioriting the well-being of all employees. They encourage and support career development